RAM Tester (IST-6500)

• Programmable downloading allows extensive output driving tests
• Stop on error/step through on error displays faulty address and bit location
• Identifies and tests DRAM, SIMM, and IC card with different pin and memory architecture
• Detection and trouble-shooting features of faults in SIMMs and IC cards
• High precision access time measurements with 2ns resolution
• Offers DRAM input leakage current testing
• Stand alone or PC-based interface
• DMA and high speed hardware test circuitry reduces testing time to 0.9s/MB/ pattern
• Supports 2 or 4k DRAM Refresh

GENERAL DESCRIPTION:

The IST-6500 is a low cost, fully programmable tester for functional and parametric testing of DRAM, SRAM, VRAM, and SIMM devices up to 144 bits wide and 64 MB in size. The 6500 offers four different ways to automatically measure the access time of these devices from 2ns to 160ns with a resolution of 2ns. The DRAM timing parameters are programmable at the resolution of 1ns to allow for testing DRAM, SIMM, or VRAM at their required operating speeds, thus providing real time test conditions. The programmable dynamic loading combined with high speed dual threshold comparators allows the user to program the DUT output loading across a wide range of operating conditions. This test is especially critical in SIMM devices, since they must often drive large capacitive and low resistance loads. The 6500 is equipped with a RS-232 port for PC interface and an Automatic Handler Interface with "Bin Sort" feature that allows the unit to sort devices based on the value of a selected device operating parameter which makes it ideal for engineering component characterization or fast "GO/NO GO' production testing.

The 6500 allows the user to easily program and store up to 100 different user defined test routines for future execution. These test routines allow automatic conduct of measurement or Go/No Go tests of the various operating parameters of a device including access time, operating current, stand-by current, data retention current, output loading, DUT power supply, timing parameters, test patterns, and logic threshold levels. Of course, the preset limits for the parameters required to conduct a GO/NO GO test can also be stored in the programs. With a group of elaborate memory test patterns and the option of short/long test pattern selection, the 6500 can detect the most common RAM failures in the shortest time. The data test pattern includes: All Ones, All Zeros, Checkerboard and Compliment Checkerboard, Marching Ones, Marching Zeros, Column Disturb, Sliding Diagonal, and Moving Inversion. These patterns can detect shorts, opens, or uniqueness fault in memory cells and address lines. Other problems such as faults with cell interactions, sensor amplifier interactions, and noise sensitivity are also detected.