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Advantages of the IST-6500 RAM Tester

  1. Offers real time functional test for DRAM and SIMM

    The accurate and repeatable generation of the timing intervals of the RAS/, CAS/, and WE/ with Row and Column address are extremely important in dynamic memory testing which requires not only testing of the function, but also the of the timing parameters. This is especially true as today's circuits utilize ever faster memory applications. DRAM with timing quality problems can cause computer "lock-up" after several hours of operation. Failure to test the required timing parameters may result in the device passing the functional test in the tester but failing in the circuit board during operation.

    In order to measure a correct and accurate access time (Trac) of DRAM also successfully latch the Row and Column address with each strobe of the RAS/ and CAS/ signals, the timing parameter Trad and Trcd must be carefully set within the minimum and maximum limits according to the manufacturers or the circuit timing specifications. The 6500 allows you to program these two most restrictive timing parameters Trad (RAS to column address delay) from 1 ns to 39 ns and Trcd (RAS to CAS delay) from ins to 99 ns, both with ins resolution. The Tasr, Trah, Tasc, Tcah timing parameters are also internally controlled. The software deskew feature can vary the WE/ signal, allowing it to generate different write cycle modes.

  2. Precision access time measurement with 2ns resolution and 5 measuring modes:

    SRAM

    (a) Tace: If address valid prior to chip enable (CE/) low, then the access time from CE/ to data valid is Tace.

    (b) Taa: If device is selected (CE/ low) prior to the address valid, then the access time from address valid to data valid is Taa.

    DRAM

    (a) Trac: (RAS Access Time) From RAS falling edge to Data Valid. The access time is Trac only when Trcd < Trcd (max) and Trad < Trad(max). The DRAM timing must be carefully set so that Trad and Trcd are within the max limit of the manufacture specification. Otherwise, the access time Trac will be increased by the amount that Trcd exceeds the max value.

    (b) Tcac: (CAS Access time) from CAS falling edge to Data Valid

    (c) Taa: (Column Address Access Time) From column address valid to Data Valid. The access time is Tcac, or Taa during the fast page mode, or either Trad or Trcd is greater than the manufactures max limit.

  3. Built-in programmable dynamic loading and dual threshold, ultra fast comparators

    It allows the user to program the DUT output loading with separate sinking current (IoL) and sourcing current (IoH) from +/- 0.1 ma to +/- 25 ma. The logic threshold voltage (Vol & Vol-I) of the comparators can also be programmed individually from 0.1 V to 4.5 V. This test can detect any out of specification device in output driving capability. It is especially useful in testing SIMMs or devices in memory arrays which must often drive high capacitance and low resistance loads on the data bus.

  4. Employs DMA and high speed hardware test circuitry to greatly reduce the testing time

    The 6500 uses the DMA to perform the Write and Read operations at 14 MHz. During the Write cycle, the DMA writes the same data pattern to the DUT and a reference Known Good memory. Then, during the Read cycle, each corresponding data output is compared by an Exclusive-OR circuit to determine the uniqueness of the data. For example, the testing time for a 1 Meg. device takes 0.7 sec / pattern.

  5. Provides basic, intensive, user defined and quick check patterns

    Creating one single perfect test pattern to detect all possible memory faults is impossible. The IST-6500 efficiently maximizes the effectiveness of testing by utilizing groups of industry standard patterns that individually focus on subsets of all possible faults.

    1. Basic (short) test pattern includes the checkerboard (alternating ones and zeros), complement, Diagonal and double checkerboard. It uses the shortest time to examine either cell opens, shorts or interaction, the ability to store ones and zeros and the function of the chip Enable or output Enable. It also checks the address or data lines open, short and uniqueness faults of the address decoder.

    2. Comprehensive (long) test pattern includes all of the basic test patterns plus, All Marching Ones, Marching Zeros, Slide, Row/Column Disturb, Fastest address axis for X or Y. These patterns can detect shorts, opens or uniqueness faults in memory cells and address lines. pattern sensitivity or sensor amplifier interaction are also detected.

    3. SIMM Quick Check Test Pattern tremendously reduces the testing time by reducing the number of the test pattern applied to the DUT. This test is primarily designed for testing the memory module or memory devices which must have high confidence in reliability. This pattern quickly checks for the most common sources of memory module failure which 96% of the time are due to manufacturing failures such as solder bridges, open or broken PCB traces or through holes, electro-static damage and improper PCB layout. This test pattern can jump through the entire memory range of the DUT to detect the faults that appear on Data Input/Output, address lines and control signals. This test mode is only applied when all the memory devices on the SIMM have been tested to their specifications by manufacturers or tested by the 6500 with basic or intensive test pattern prior to their assembly on the printed circuit board.

    4. User Defined Test Pattern The user can select any test pattern that is provided by the 6500 such as All Ones, All Zeros, Checkerboard, Complement Checkerboard, Diagonal, Marching One or Zero, Moving Inversion Row / Column disturb and user entered data.

      The refresh test of DRAM is combined from the (a), (b) and (d) test pattern by writing the data pattern to the DUT. After a programmable time delay of no activity, the data is then read back to check for uniqueness. The address and data lines Walking tests are applied in all test patterns.

  6. Offers the DRAM input leakage current test and the current parameters measurement or go/no go test for operating current (Icc1), standby current (Icc2), and data retention current Idr).

    This provides the user with the capability to screen out the marginal devices that drain more current than normal. Usually, this indicates some degree of malfunction in a sense amplifier or leakage in the internal circuitry of the device. The 6500 can automatically program the supply voltage to 3.0 V and measure the data retention current for CMOS SRAM in the uA range.

  7. Universal Mainframe and family plug-in module design

    This greatly reduces the overall cost of testing equipment, number of test adaptors required, and allows the 6500 to meet the demands of the rapidly changing memory device market. The 6500 mainframe contains all the necessary hardware circuitry to perform the testing and measuring for all the features provided. The plug-in modules are grouped by DUT family type (i.e., SRAM, SIMM, DRAM, etc.) and each DUT in the family module is carefully sorted by its memory size and pin out configuration with built-in electronic routing networks for the address lines. No personality module or adaptor is required for testing each device. All that may be necessary is a low cost universal test socket adaptor for different package types such as SOJ, ZIP, and PLCC packages. This provides the greatest convenience and saves the cost and hassle of having separate test adaptors for each device.

  8. Stores up to 100 user defined test programs for "one time set-up" capability

    These test programs allow automatic conduct of measurement or go/no go test of the various operation parameters of the device including the type of access time, current, test pattern, operation mode (early write, late write, page mode, etc.) and the programmed range or data for output loading, DUT supply voltage, logic threshold and DRAM timing control parameters.

  9. Automatic handler and PC interface

    The 6500 is compatible with the industry standard handler interface both in pulsing and level format for fast and automatic production test. It also allows for "bin sorting" of parts according to the test result. The RS-232C PC based interface with Windows software is also provided for detailed test result display or failure analysis, especially in SIMM testing.

  10. High convenience SIMM and IC card testing

    1. Access Time: The 6500 automatically measures the access time of every single chip in the SIMM, then displays the slowest measurement as the SIMM access time. With PC interface, the access time and test result of each chip can be individually displayed.

    2. Diagnostic feature for troubleshooting:
      1. Automatic detects and displays the mnemonic sign of any stuck line in address, data bus and control signals.
      2. Bus mnemonic sign. If two or more signals are shorts together the tester displays all its mnemonic signs. For example: If A2, D7 and WE/ are shorted, the LCD display will show A2, D7 and WE/ as long as this point is probed.
      3. Looping on failure: As a failure is detected the tester can exercise the full range of the address bus, control signals and data bits. The user can then use an oscilloscope to troubleshoot and trace the signal.

    3. Automation: IST offers turn key operation for automatic IC or SIMM testing by providing the automatic handler and PC based interface software. As the SIMM handler employs a panel testing approach, it greatly simplifies the operation, reduces down time, and increases through put.

      SOJ IC Interface Image
      Interface to SOJ IC automatic handler


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